This application claims the priority benefit of Taiwan application serial no. 88117662, filed Oct. 12, 1999.
1. Field of the Invention
This invention relates to a digital circuitry, and more particularly, to a non-integer frequency divider capable of converting an original clock frequency into a target clock frequency equal to the original clock frequency divided by a non-integer number. The non-integer frequency divider of the invention can be used, for instance, on a PC mother-board to produce a set of different clock frequencies to drive various components of different clock specifications on the motherboard, such as CPU, memory, and peripheral devices.
2. Description of Related Art
In a computer system, the CPU serves as the main control and computation unit. The operation of a CPU is driven by a clock signal whose frequency determines the speed of the CPU. On a PC motherboard, however, a number of clock signals of different frequencies might have to be provided to drive various components of different clock specifications on the motherboard, such as CPU, memory, and peripheral devices.
Presently, PC speeds are rated at 266 MHz, 300 MHz, 350 MHz, 400 MHz, 450 MHz, or higher. One problem to the use of these high-speed CPUs, however, is that other components on the motherboard, namely the memories and peripheral devices, are still operating at low clock frequencies. For this reason, when a high-speed CPU is used in conjunction with a low-speed memory unit or peripheral device, the motherboard should be capable of generating a number of different clock frequencies.
The CPU communicates with the peripheral device via a dedicated I/O bus architecture. By the ISA (Industry Standard Architecture) standard, the I/O bus is operated at 8.33 MHz, which is obtained by dividing the 66 MHz main memory clock signal by 8. The reason why this slow-speed architecture is still in use is that it allows compatibility with old ISA-based function cards.
Newer I/O bus architectures are faster in speed than ISA, but they are still slower than the main memory. The PCI (Peripheral Component Interconnect) architecture can operate at 33 MHz, which is half of the 66 MHz main memory clock signal.
Presently, PC motherboards typically utilize a PLL (phase-locked loop) circuit for the generation of the various required clock frequencies. If a first clock frequency is an integer submultiple of a second clock frequency, the first clock frequency can be easily generated by using a frequency divider to divide the second clock frequency. However, this may not always be the case. For example, the motherboard may require the use of the clock frequencies of 66 MHz, 100 MHz, and 133 MHz, of which the 100 MHz clock frequency is not an integer submultiple of 133 MHz, which would make the PLL circuit quite complex in structure.
For instance, the use of the AGP (Advanced Graphic Port) 4X circuitry requires the use of the clock frequencies of 266 MHz, 200 MHz, 133 MHz, 100 MHz, and 66 MHz. One scheme to obtain these clock frequencies is to generate an original clock frequency of 800 MHz and then divide this original clock frequency respectively by the integer numbers of 3, 4, 6, 8, and 12. One drawback to this scheme, however, is that it makes the PLL circuit quite complex in structure with huge power consumption.
The object of this invention is to provide a non-integer frequency divider, by which a target clock frequency can be obtained by dividing an original clock frequency by a non-integer number so that the above-mentioned set of clock frequencies of 266 MHz, 200 MHz, 133 MHz, 100 MHz, and 66 MHz can be obtained, for example, by dividing an original clock frequency of 400 MHz by the non-integer and integer numbers of 1.5, 2, 3, 4, and 6.
Another object of this invention is to provide a non-integer frequency divider which is less complex in circuit structure than prior art for the generation of a set of different clock frequencies.
Yet another object of this invention is to provide a non-integer frequency divider which consumes less power and is less sensitive to the noise than prior art.
In accordance with the foregoing and other objectives, the invention proposes a new non-integer frequency divider. The non-integer frequency divider of the invention is designed to convert an original clock frequency into a target clock frequency equal to the original clock frequency divided by a non-integer number. To do this, the original clock should be first phase-shifted into a predetermined number of phase-shifted versions of the original clock with a predetermined phase difference. Then, a plurality of edge-triggered clock signal generators are used to receive the original clock and its phase-shifted versions as input signals for generating responsively a plurality of edge-triggered signals which are synchronized in rising and falling edges with the original clock frequency and its phase-shifted versions.
Next, a synthesis circuit is used to receive the edge-triggered signals as input signals for synthesizing the edge-triggered signals into an output signal serving as the intended target clock. The synthesis circuit includes: a set of XOR gates, each receiving two of the edge-triggered signals from the plurality of edge-triggered clock signal generators as input signals, for performing an XOR logic operation on each set of two received edge-triggered signals to thereby generate a set of duty-cycle signals and an OR gate having a set of input ends. Each input end is connected to the output port of each of the XOR gates, for performing an OR logic operation on the received duty-cycle signals from the XOR gates, with its output serving as the intended target clock.
With the non-integer frequency divider of the invention, a 266 MHz clock frequency can be obtained by dividing an original clock frequency of 400 MHz (rather than 800 MHz as in the case of the prior art) by a non-integer number of 1.5, while the clock frequencies of 200 MHz, 133 MHz, 100 MHz, and 66 MHz can still be obtained by dividing the 400 MHz frequency by the integer numbers of 2, 3, 4, and 6. Therefore, the invention allows the required PLL circuitry to be less complex in structure, less power-consuming, and less susceptible to external noise.
The invention can be realized by using an oscillator capable of generating the original clock and the shifted versions of the original clock frequency. In this case, the non-integer frequency divider further includes a first edge-triggered clock signal generator, which is capable of being triggered by the original clock frequency to thereby generate a first positive edge-triggered signal and a first negative edge-triggered signal; a second edge-triggered clock signal generator, which is capable of being triggered by the shifted version of the original clock frequency to thereby generate a second positive edge-triggered signal and a second negative edge-triggered signal; and a synthesis circuit for synthesizing the first and second positive edge-triggered signals and the first and second negative edge-triggered signals into an output signal serving as the intended target clock frequency.